1. Field of the Invention
The present invention relates generally to non-volatile memories and in particular to an erasable programmable read only memory or EPROM having a segmented array of memory cells so as to provide high performance and a method for controlling the memory.
2. Background Art
There has been a tendency to reduce the size of EPROMs so as to increase data storage capacity and to increase the speed of operation. Referring to the drawings, FIG. 1 shows a conventional EPROM memory array with control circuitry removed. The array, which has a capacity of 1 Megabit, is comprised of N channel cells of the floating gate variety, with each cell including a drain, a source, a channel region intermediate the drain and source and a polysilicon floating gate overlying the channel region and insulated from the region. A polysilicon control gate overlies the floating gate and is insulated from the floating gate. For purposes of definition, the drain region of the disclosed N channel cells 10 is the most positive of the drain/source regions when the cell is being read.
The floating gate cells 10 are arranged in 1024 rows and 1024 columns to form a 1 megabit array. In the exemplary array, all of the cells 10 have their source regions connected to circuit common. All of the cells 10 located in a particular column have their drain regions connected to a common bit line BL1-BL1024. The bit lines may be implemented by way of a metal bit line or by way of a buried doped semiconductor line. All of the cells 10 located in a particular row have their control gates connected to a common word line WL1-WL1024. The word lines are typically implemented by way of doped polysilicon lines.
Programming of the individual cells is accomplished by applying a relatively high positive voltage to the bit line associated with the cell 10 to be programmed. In addition, a positive voltage is applied to the word line associated with the cell to be programmed. The resultant electric field causes electrons to travel from the grounded source region to the positive drain region. Some of these accelerated electrons will acquire sufficient energy to pass through the insulating oxide intermediate the channel and the floating gate and be deposited on the floating gate. This mechanism, sometimes called hot electron injection, places a negative charge on the floating gate which will increase the threshold voltage of the cell above that when the cell in the erased state.
Reading of the individual cells is accomplished by applying a small positive voltage to the bit line associated with the cell to be read. In addition, a positive voltage is applied to the word line associated with the cell. In the event the cell being read is in an erased state, the positive voltage applied to the word line will be in excess of the erased threshold voltage of the cell so that the cell will be rendered conductive. Current will flow from the bit line and through the cell to the circuit common. A sense amplifier connected to the bit line (not depicted) will detect the current flow thereby indicating the erased state of the cell being read. In the event the cell had been previously programmed, no current will flow, thereby indicating the programmed state of the cell being read.
The cells 10 are erased by subjecting the cells to ultraviolet light. Typically, the integrated circuit package containing the array is provided with a window through which the light may pass. The light will cause any charge present on the floating gate to be removed. No voltages are applied during U.V. erase.
Memory program and memory erase operations require at least an order of magnitude more time than do memory read operations. For this reason alone, EPROM devices are primarily intended to function as read mostly devices. That is, once the device has been programmed, it is anticipated that almost all of the subsequent operations will be read operations. Thus, the speed of memory read operations essentially determines the overall speed of the EPROM for all practical purposes.
One of the primary limitations on reading speed is the inherent capacitance associated with the memory bit lines. Some of this capacitance is attributable to the capacitive coupling between the associated bit line and the surrounding structure, with the remainder of the capacitance being attributable to the capacitance of the drain region of all of the cells connected to the bit line. This capacitance is particularly large in the exemplary FIG. 1 array in that the bit line extends the full length of the array and is connected to each of the 1024 cells located in the associated array column.
The delays associated with the capacitance are exacerbated when the bit lines have a significant resistance. The resultant large RC time constant significantly impedes the speed of memory read operations, particularly when the bit line is implemented in the form of a doped semiconductor line, either diffused or ion implanted, rather than a metal line.
One approach to overcoming such speed limitation is to use memory cells that produce large currents when read. These large currents decrease the time necessary to charge and discharge the bit lines. However, large cell currents inherently require large geometry cells. Large geometry cells obviously result in a decrease in the number of cells which can be implemented in an integrated memory device and further result in the undesirable parasitic capacitance previously discussed.
The effects of bit line capacitance can be reduced by segmenting the bit line. By way of example, FIG. 2 shows part of a prior art memory cell array utilizing a segmenting technique. Only part of a single array column is depicted, namely, a column associated with a bit line BL1. The array includes a Segment 1 comprising rows 1-32 of cells 10 and a Segment 2 comprising rows 33-64 of the cells. Other segments can be added as required and the size of the segments can be increased to include 64, 128, etc. rows in each segment. Further, the number of columns present in each segment can be increased.
Each segment is connected to the associated bit line BL1 by a segment select transistor, with Segment 1 being connected by way of transistor 12 and Segment 2 connected by way of transistor 14. Depending upon the read address, only one of the segments is selected at one time by way of appropriate segment select transistors SS1, SS2, etc. Thus, the total capacitance associated with the bit lines is substantially reduced. By way of example, if Segment 1 is selected, select transistor 12 is made active with the remaining select transistors being maintained off. Thus, only the capacitance associated with the drains of cells 1-32 must be charged and discharged during the read operation. Bit line BL1 still extends the full length of the array, but the capacitance attributable to the bit line alone is significantly smaller than that associated with the drain regions of the cells 10 of the non-selected segments.
There has also been a tendency in the prior art to reduce the area required of a memory array by alternating metal bit lines and diffused semiconductor bit lines. Since metal bit lines require much more area to implement than do semiconductor bit lines, the use of alternating metal and semiconductor lines reduces the area of each cell significantly. Such arrays are sometimes referred to as alternate metal virtual ground or AMG arrays.
FIG. 3 shows an exemplary prior art AMG array of memory cells 10. The array includes multiple segments including a Segment 1 comprising rows 1-64 and columns of cells 1-6. An actual array would include many more columns. The next segment is Segment 2 and includes rows 64-128, with only one row being depicted. Typically, there would be additional segments in the AMG array.
The cells in a row are arranged in pairs, with each pair sharing a common source region. By way of example, adjacent cells 10A and 10B located in the row associated with word line WL2 include a common N type source region. Cell pair 10E and 10F located in the row associated with word line WL3 also share a common N type source region diffusion which is connected by a buried N type semiconductor bit line BLB to the common source region diffusion of cells 10A and 10B. Similarly, cells 10B and 10C in adjacent cell pairs have a common N type drain region diffusion which is connected by a buried N type semiconductor bit line BL2 to the common drain region of cells 10F and 10G.
Alternate bit lines, including line BL1, BL2 and BL3 are each connected in parallel with an overlying metal track (not shown). The metal tracks are connected to the buried bit lines by way of contacts 16 located at the top and bottom of each segment.
Each segment of the conventional AMG array has an associated set of segment select transistors SSN which are controlled by complementary segment select signals SN and SN. The segment select signals are controlled by address decoding circuitry so that only one of the array segments will be enabled during a read or write operation. When Segment 1 is enabled, a selected one of signals S1 and S1 is active and the other segments select signals SN and SN are inactive. Similar segment select transistors are located on the opposite side of each segment and are connected in parallel with the transistors located at the top of the array and are driven by the same select signal SN and SN. This parallel arrangement of segment select transistors at opposite sides of the bit lines tends to reduce the effect of bit line resistance by one-half.
Operation of the AMG array can best be described by way of example. Assume that cell 10B is to be read. Control circuitry (not depicted) will cause a positive voltage to be applied to bit line BL2 by way of a load circuitry (also not depicted). This voltage will thus be applied directly to the drain region of cell 10B. The control circuitry will also ground bit line BL1. The remaining bit lines BLN are also maintained at the same positive voltage as bit line BL2. Segment select signal S1 will be active (high) and S1, by definition will be inactive. Thus, segment select transistor SS1 will be rendered conductive and transistor SS1 will remain off. Conductive transistor SS1 will connect the source region of cell 10B to grounded bit line BL1. In addition, the control circuitry will connect a positive voltage to word line WL2.
Assuming that cell 10B is in an erased state, the above conditions will render cell 10B conductive. Current will flow from bit line BL2, through the cell, into bit line BLB, through transistor SS1 to the grounded bit line BL1. Sense circuitry will detect the resultant change in voltage at the load connected to bit line BL2 thereby sensing the state of cell 10B.
The deselected word lines of the array are all grounded so that the cells of the deselected rows will remain non-conductive irrespective of programmed state. With respect to cell 10A in the selected row, this cell will remain non-conductive since both the drain and source of the cell are at ground potential. This is also true of the cells in the selected row to the left of selected cell 10A. Cell 10C will remain non-conductive since conductive transistor SS2 will cause both the source and drain to be at the same positive voltage. With respect to cell 10D, as previously noted, the deselected bit line BLN, with the exception of line BL1, are at the same positive potential as bit line BL2 so that both the drain and source of the cell are at the same potential as are the other cells in the row to the right of cell 10D. Thus, these deselected cells will remain nonconductive.
Programming of selected cell 10B is accomplished by bringing bit line BL2 to a positive voltage and grounding the remaining bit lines BLN through a high impedance load. A large positive voltage is applied to the selected word line WL2 and the deselected word lines are grounded. Again, select signal S1 is made active and S1 inactive so that line BLB connected to the source of cell 10B is at ground potential and the drain connected to bit line BL2 is at a positive potential. This combination of voltages will cause cell 10B to be programmed. The cells in the deselected rows will not be programmed since the deselected word lines are all grounded. With respect to cell 10A in the selected row, the source and drain will be at the same low potential so that programming will not take place. Cell 10C will not be programmed because the drains and sources of the cells will be at the same high potential due to transistor SS2 being conductive. Cell 10D will have its source at a high potential and its drain presented with a high impedance to ground so that it will also not become programmed.
It can be seen that when successive memory cell reads take place, it is likely that one or more of the bit lines BLN will have to switch between high and low level states. Although the bit lines have a relatively low resistance by virtue of the overlying metal bit track connected in parallel, the bit lines extend over the full length of the array, interconnecting each of the array segments, including the relatively high capacitance of each cell of the array connected to the bit lines. Since, as previously noted, the time required to carry out read operations is the limiting factor in the overall speed performance of this type of read mostly memory, it can be seen that the AMG array speed is reduced.
The AMG array is capable of achieving a high cell density but suffers from a speed disadvantage due to the bit line capacitance previously described. A memory array which provides both the density of AMG arrays, but minimizes the speed shortcomings of such arrays would be highly desirable. The subject invention achieves both of these goals. These advantages of the subject invention and other advantages will be apparent to those skilled in the art upon a reading of the following Detailed Description of the Invention together with the drawings.